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 ELEKTRONIK |
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Geschützte Register
(time protected control registers)
Diese Register können nur während der ersten 64 Taktzyklendes E-Taktes nach einem RESET beschrieben werden.
| INIT | bit 7-4: | RAM3, RAM2, RAM1, RAM0
position direct page at 4k-boundaries
(default = 0000, RAM = $0000-$00FF) |
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| bit 3-0: | REG3, REG2, REG1, REG0
position Register block at 4k-boundaries
(default = 0001, REG = $1000-$103F) | TMSK2 | bit 1-0: | PR1, PR0
prescaler of main timer
(default = 00, ps = 1) |
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OPTION | bit 5: | IRQE
IRQ edge or level sensitive
(default = 0, level sensitive) |
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| bit 4: | DLY
delay after coming out of STOP power saving mode
(default = 1, wait 4000 cycles to stabilize crystal oscillator) | | bit 1-0: | CR1, CR0
COP timer rate on 215 base
(default = 00, tr = 1) |
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